Intel unveils D-Series accelerator: 480 GB memory, no HBM

Intel has officially launched the D-Series GPU accelerator family, developed under the codename Crescent Island, at the OCP Global Summit. While rivals chase raw peak performance, Intel is positioning the product around exceptional memory capacity — up to 480 GB of LPDDR5X — and efficiency for running inference in existing data centers.

Xe3P architecture: 32 cores and 256 matrix engines

The technical foundation is the Xe3P architecture, which Intel detailed for the first time at Hot Chips. The die contains 32 Xe-Cores organized into four Compute Slices of eight cores each. Alongside the classic vector units (XVE) are 256 XMX matrix engines for accelerating matrix math, a unified 32 MB L2 cache, and a media engine with four encoders and four decoders for multimodal workloads. The architecture adds hardware support for activation functions such as Sigmoid and Tanh, plus a Same Address Multi-Queue mechanism to improve parallelism.

Memory over bandwidth: the LPDDR5X choice

The most notable design decision is the abandonment of HBM in favor of LPDDR5X. Intel's reference card ships with 160 GB, but the design enables partners to build accelerators with up to 480 GB. A 1,280-bit interface combined with LPDDR5X-9600 delivers a theoretical 1.536 TB/s of bandwidth (Intel quotes 1.5 TB/s officially). That is significantly below leading HBM-based accelerators, but Intel argues that for inference with long context windows and multi-agent workloads, capacity is the critical constraint — the KV cache demands large volume for storing intermediate results.

Performance figures: 1.3 petaflops FP8, 350 W

Intel cites 1.3 petaflops at FP8 precision, with support for FP4 and FP64 for applications requiring higher precision. The power envelope stands at 350 W in a PCIe form factor. The company states a single accelerator can run models up to 300 billion parameters, and an eight-accelerator system supports models exceeding one trillion parameters, though Intel does not specify the quantization level or constraints under which those numbers were achieved.

Market focus: inference at scale, not training

The positioning is clear: Intel is not trying to go head-to-head with H100/H200 or MI300X on raw training performance. The D-Series targets enterprises running heavy inference — large language models, multi-agent systems, long contexts — that want more memory within a standard PCIe power and infrastructure envelope. The trade-offs are known: lower bandwidth than HBM, and no official quantization data for the largest models. The practical question is whether partners will adopt the flexible up-to-480 GB design, and at what price.