Anonymous developer claims to reverse-engineer Taalas patents and bypass bitROM

An anonymous developer posted on X over the weekend describing a half-year project in which the author, identifying as unemployed and unfunded, attempted to reverse-engineer the intellectual property of Taalas. The author asserts that the architecture developed requires one hundred times fewer memory fetches (memfetches) than Taalas’s bitROM approach and achieves better results through software quantization that surpasses what Taalas’s hardware team has implemented. These statements are presented as unverified claims from a single source, without published benchmarks or peer review.

From checkpoint to GDS in about 7,000 lines

The core of the project is a compiler that takes a checkpoint from Hugging Face, applies quantization to the model, and then lowers the weights through metal layers to the register-transfer level (RTL) and GDS stages, including design-rule checking (DRC), synthesis with Yosys, and place-and-route extraction (PEX). The resulting electrical representation performs matrix-vector multiplication directly from the original checkpoint. The implementation draws on technical papers from Cambricon, and the entire flow is written in roughly 7,000 lines of human-readable code. No source code, documentation, or proof of execution on real silicon has been released.

Request for 7-nanometer PDK or EuroPTW shuttle

At the end of the post the author asks for connections to a foundry that provides a 7-nanometer process design kit (PDK), or a cheap shuttle run through EuroPTW, a program that lets researchers and startups produce small runs at reduced cost. He emphasizes he is “without money and unemployed,” framing the request as an effort to move the project from simulation to physical fabrication. Without access to a PDK or shuttle, the flow remains at the logical design and simulation stage.

Performance claims: 40,000 tokens per second and the future of perplexity to picojoule

The author cites a target of 40,000 tokens per second and labels the direction “the future of perplexity to picojoule,” a metric that would combine model quality with power consumption. The numbers are not accompanied by measurement conditions, model size, temperature, or a defined baseline. The post tags three accounts—@itsclivetime, @zerohedge and @zephyr_z9—but it is unclear whether they are technically involved or merely invited to observe.

Status: large claims, no verification

At present the description is a self-report from an individual, lacking open-source code, a synthesis report, post-silicon results, or institutional backing. The flow—from Hugging Face checkpoint through quantization to RTL/GDS/PEX—is theoretically possible and has been explored in academia and industry, but the leap to “one hundred times fewer memfetches” and 40,000 tokens per second requires proof. Until open weights, hardware runs, or at least a signed PEX simulation are made available, the story remains an interesting research direction rather than a validated product.