Nvidia opens NVLink to custom accelerators with NVLink Fusion

AI factories are judged by output metrics—tokens per second, tokens per watt, cost per token, utilization and availability—rather than by accelerator count. Nvidia says the route to higher output runs through infrastructure engineered as a complete factory, not as a collection of discrete accelerators. Companies that build their own XPU (application-specific accelerators) encounter a fundamental bottleneck: designing and developing the entire platform—from scale-up and scale-out networks through rack architecture to manufacturing software and supply-chain logistics—is complex and costly enough to delay market entry.

NVLink Fusion is intended to break that constraint by attaching custom XPU to Nvidia’s proven infrastructure, allowing developers to concentrate on their own innovation while the remainder of the stack relies on mature technology. The sixth generation of NVLink supplies a scale-up fabric for 72 accelerators within a single domain. Nvidia claims end-to-end latency between accelerators is 3 times lower than shelf-based Ethernet solutions, and packet rate is 10 times higher. GB300 NVL72 systems already demonstrate markedly higher throughput and better interactivity than configurations lacking NVL72, and the roadmap foresees domains of up to 1,152 accelerators with co-packaged optics.

NVLink-C2C, part of the package, connects XPU to Nvidia Vera processors or other ecosystem CPUs, delivering energy efficiency 6 times higher than a PCIe interface. This removes a barrier between control logic and compute, which is critical for agentic systems that require tight coordination between components.

Teams building custom XPU often under-invest in turning silicon innovation into data-center deployment: fast CPU-scale-up interfaces, network solution identification and validation, compute board and switch design, rack architecture including cooling and power, security, storage, and complex supplier-ecosystem management. NVLink Fusion arrives with an ecosystem designed for rapid development, integration and deployment, spanning ASIC design partners, CPU pathways, and optical interconnect IP. The MGX rack architecture and the MGX-based supply chain (such as Vera) are also available to these efforts.

Tim Wilson, vice president and general manager of silicon data-center engineering at Intel, said, “NVLink Fusion enables customers to choose CPU architecture, performance level and software capabilities that match their workloads, without being locked into a single stack.”