Waymo unveils new computing architecture delivering 20× power in eight years with 5-nm ASIC

Waymo released the first technical details of the embedded computing architecture that powers the next generation of Waymo Driver. The system is built around a dedicated ASIC manufactured in a 5-nanometer process in partnership with AMD. Waymo reports more than 200 million miles (≈322 million km) of fully driver-less autonomous driving, a dataset that guided the design to meet three fundamental requirements: real-time responsiveness, extreme physical durability, and hardware-level redundancy.

According to Waymo, the vehicle’s compute stack handles workloads that would be impressive even in a data center, yet must operate within a car under strict real-time constraints. Unlike traditional driver-assistance systems, there is no human driver to intervene, so the architecture is organized around three non-negotiable principles. First, responsiveness: the system makes driving decisions in single-digit milliseconds from the first pixel to the actuation command, using advanced ML models that construct a high-resolution understanding of the environment. Second, durability: the hardware is engineered to survive vibrations, shocks and extreme temperatures, and is integrated directly into the vehicle’s liquid-cooling loop to maintain peak performance in both Midwestern winters and Phoenix heat. Third, redundancy: two independent compute engines run in parallel at full load, with one taking over instantly if the other fails.

The shift from off-the-shelf components to custom-designed silicon required a complete redesign of the physical and architectural layout. The result is a densely integrated system that delivers massive processing capability without compromising passenger experience: maximal battery efficiency, preserved cargo volume and quiet operation. Waymo notes a 20× increase in raw compute power over 8 years, complemented by deep software optimization that extracts efficiency from that capacity. The architecture is described as ML-primary: the neural-network core runs with minimal latency, while non-ML tasks such as scheduling, data traffic management and logging are handled by the best available CPU, GPU and accelerators, forming a balanced heterogeneous system.

At the heart of the new platform is the 5-nanometer ASIC, the first of several custom components Waymo is developing. The chip is purpose-built to ingest, fuse and execute advanced neural networks on raw sensor data in real time. The joint development of silicon, sensors and algorithms pushes the limits of sensor fidelity, bandwidth efficiency and quantization, enabling a range of models from lightweight convolutions to dense transformers. While the ASIC is a single element in the stack, it serves as the initial “brain” that captures the raw data stream before it reaches the central ML core.

AMD joins as a partner contributing its open-computing portfolio to power the next generation. The move reflects a view that physical AI will not be decided by a single accelerator or closed stack, but by an open ecosystem that permits flexible integration of optimal components for each task. Waymo emphasizes that the new chip is only one of several custom parts under development, and that the overall architecture is built to allow component replacement and upgrades over time, a strategy that sets it apart from locked-in proprietary solutions.